1. Field of the Invention
The present invention relates to providing frequency compensation, and more particularly, to a feedback-controlled system (e.g., an LDO voltage regulator) using a current generating apparatus capable of minimizing the DC offset of an output current used for frequency compensation.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a first conventional LDO (low dropout) voltage regulator 10. The LDO voltage regulator 10 comprises a pass transistor MP, a feedback voltage divider 11, and an error amplifier 12. The connections between the pass transistor MP, the feedback voltage divider 11, and the error amplifier 12 are shown in FIG. 1. The input terminal Nin of the LDO voltage regulator 10 is coupled to a supply voltage VDD. The output terminal Nout of the LDO voltage regulator 10 is coupled to a loading stage, which is equivalent to a resistor RL connected with a capacitor CL in parallel. Please note that the terminal Ng has a parasitic resistor RPAR and a parasitic capacitor CPAR, where the capacitor CL has an equivalent series resistance of RESR connected to the capacitor CL. Accordingly, it is well-known that there are two low-frequency poles that need to be taken into account when determining the closed-loop transfer function of the frequency response of the LDO voltage regulator 10. In order to guarantee the phase margin of the LDO voltage regulator 10 will be greater than 45 degrees, a zero is introduced to compensate the phase contribution of the two low-frequency poles. Normally, the series combination of the capacitor CL and the equivalent series resistance RESR generates a zero ωESR that provides the LDO voltage regulator 10 with proper phase margin. However, in some conditions, the equivalent series resistance RESR fails to provide proper phase margin for the LDO voltage regulator 10. Please refer to FIG. 2. FIG. 2 is a frequency response diagram of the LDO voltage regulator 10 with various load currents IL at fixed ωESR. For brevity, three Bode plots 21, 22, and 23 are shown in FIG. 2, which correspond, respectively, to light load current, proper load current, and heavy load current of the LDO voltage regulator 10. Furthermore, there are three poles and one zero for each of the Bode plots 21, 22, and 23, in which the first pole ωp1 is mainly concentrated at the output terminal Nout, the second pole ωp2 is mainly concentrated at the terminal Ng of the transistor MP, and the zero is ωESR. When the load current IL varies from the heavy load status to the light load status, the first pole ωp1 decreases roughly and the second pole ωp2 decreases as well, as shown in the Bode plots 21, 22, and 23 of FIG. 2. Furthermore, three of the Bode plots 21, 22, and 23 have poor phase margin in this case. There are at least three drawbacks by utilizing the zero ωESR to compensate the pole of the LDO voltage regulator 10. Firstly, the high-frequency bypass capacitor Cgdpass placed in parallel with the capacitor CL provides another pole with the zero ωESR of the capacitor CL, in which the new pole will further decrease the phase margin of the LDO voltage regulator 10. Secondly, the equivalent series resistance of RESR of the capacitor CL is not properly specified in many cases and varies with temperature. As a result, the zero ωESR cannot be predicted easily. Thirdly, owing to some advantages of ceramic capacitors, such as low RESR, less expense, and compact printed circuit boards, using the ceramic capacitor is becoming more popular. However, it is hard to generate a proper zero ωESR with the low RESR.
Besides utilizing the zero ωESR to compensate the pole of the LDO voltage regulator 10, there are various other frequency compensation means taught in the prior art. Please refer to FIG. 3. FIG. 3 is a diagram illustrating a second conventional LDO voltage regulator 30 having a prior art frequency compensation implemented therein. The LDO voltage regulator 30 shown in FIG. 3 is equivalent to applying the prior art frequency compensation to the LDO voltage regulator 10. The frequency compensation method of FIG. 3 is to provide a feedback path for the output voltage Vout through an additional capacitor CF, and the connection is shown in FIG. 3. The capacitor CF provides a high-frequency bypass path for the loop gain of the LDO voltage regulator 10. Then a pole-zero pair (ωp, ωz) is generated, which is represented by the following equation (1) and equation (2),ωz=1/(RF1*CF),  (1)ωp=(1+(RF1/RF2))/(RF1*CF)  (2)
According to this prior art circuit configuration, due to the fact that the resistance magnitudes of feedback resistors RF1 and RF2 have the same order, the pole ωp and the zero ωz are not far from each other as shown in FIG. 4. FIG. 4 is a diagram illustrating the frequency response of capacitive feedback frequency compensation of FIG. 3. The curve 41 represents the transferring characteristic of the frequency compensation of FIG. 3, and the curve 42 represents the phase variation of the frequency compensation of FIG. 3. Accordingly, the zero ωz contributes less phase margin for the frequency compensation of FIG. 3.
According to the reference of Chaitanya K. Chaya, and Jose Silva-Martinez, “A Frequency Compensation Scheme for LDO Voltage Regulators”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I. REGULAR PAPERS, VOL. 51, NO. 6, Jun. 2004, an improved prior art frequency compensation developed from the frequency compensation of FIG. 3 is proposed. Please refer to FIG. 5. FIG. 5 is a diagram illustrating a third conventional LDO voltage regulator 50 having another prior art frequency compensation implemented therein. The LDO voltage regulator 50 shown in FIG. 5 is equivalent to applying the improved prior art frequency compensation to the LDO voltage regulator 10. The frequency compensation of FIG. 5 is implemented using a frequency-dependent voltage-controlled current source (VCCS) 52 connected at the feedback terminal NFB of the LDO voltage regulator 50. The frequency-dependent VCCS 52 is capable of eliminating the pole ωp of FIG. 3 and generate a new zero ωz0. The new zero ωz0 is determined by the following equation:ωz0=1/(N*RF1*CF).  (3)
Therefore, the location of the new zero ωz0 can be easily adjusted by modifying the current mirror ratio N set to the current mirrors 54a, 54b or modifying the capacitance of the ground capacitor C1 of the FIG. 6. FIG. 6 is a diagram illustrating the frequency-dependent voltage-controlled current source 52 shown in FIG. 5. However, the mismatch of the current mirror 54a and the current mirror 54b, both having the same current mirror ratio N, induces a DC current ΔIB flowing into the feedback resistors RF1, RF2, and equivalently forms a mismatch resistor Rmismatch parallel with the feedback resistors RF1, RF2 as shown in FIG. 6. Hence, the output voltage Vout varies due to the mismatch resistor Rmismatch from the imbalanced current mirrors 54a, 54b. Furthermore, the mismatch of current mirrors 54a, 54b contributes considerable yield loss for chip mass production. In addition, the mismatch current ΔIB is in proportion to the current mirror ratio N of current mirrors 54a, 54b. Furthermore, as the output voltage Vout changes, the mismatch current ΔIB changes accordingly. In order to decrease the effect of the mismatch current ΔIB, the current mirror ratio N of the current mirrors 54a, 54b should preferably be lower, and the capacitance of the grounded capacitor C1 should preferably be larger. However, the larger the capacitance, the higher the production cost and chip area becomes.